(1) Field of the Invention
The invention relates to digital integrated circuits, and more particularly, to a circuit that allows a digital signal to be level shifted from a low voltage supply to a high voltage supply.
(2) Description of the Prior Art
Ultra deep submicron CMOS technologies are used to create digital integrated circuits with very high transistor densities and very high switching speeds. These submicron CMOS transistors have very thin gate oxide and very low threshold voltages. To facilitate use of ultra deep submicron CMOS processes, the supply voltage for the high-density logic core must be lowered to improve device reliability. Supply voltages of between about 2.5 Volts and 3.3 Volts, which have been typical for prior art CMOS logic devices, have to be reduced to a low voltage regime of, for example, about 1 Volt for a 0.13 micron CMOS process.
While the supply voltage of the core logic section is being reduced, the supply voltage for the input/output section of the integrated circuit must be kept at a higher level to assure adequate signal-to-noise ratio and compatibility with other devices. Where digital signals in the low voltage core must be transmitted off the integrated circuit, signal level shifting is therefore necessary. A level shifting circuit is the bridge that transforms signals from a low core voltage (VDD) to a high I/O voltage (VDDQ) and is used to increase the upper voltage swing of the low voltage signal, from low voltage to high voltage. However, the conventional level shifter does not work as the core voltage decreases down to about 1 Volt as will be seen in an analysis of the prior art.
Referring now to FIG. 1, a prior art level shifting circuit is shown. This level shifting circuit uses low voltage and high voltage transistors. Low voltage transistors, such as P138 and N134, are used in the low supply voltage VDD 72 section. High voltage transistors, such as P318 and N310, are used in the high supply voltage VDDQ 76 section. The low voltage transistors have a thinner gate oxide than the high voltage transistors. In addition, the low voltage transistors have a low threshold voltage of perhaps about 0.3 Volts for NMOS and about xe2x88x920.3 Volts for PMOS. By comparison, the high voltage devices have a threshold voltage of perhaps about 0.7 Volts for NMOS and about xe2x88x920.7 Volts for PMOS.
The prior art level shifting circuit generates buffered versions, LVINB 54 AND LVIN 58, of the input, IN 50. These low voltage signals are coupled to the gates of the high voltage NMOS devices N310 and N414. The differential pair formed by N3 and N4 combine with the cross-coupled transistors P318 and P422 to generate the level-shifted outputs HVA 60 and HVB 64. An inverter buffer is used to generate the output, OUT 68.
An analysis of the ac operation of the prior art level shifting circuit reveals a serious switching delay when the design is used in an ultra-deep submicron process. In such processes, the VDD 72 voltage is very small to facilitate the usage of very small devices with very thin gate oxides, shallow junctions, and shrinking threshold voltages. However, the important input transistors of the circuit, N310 and N414, still have large voltage thresholds. Therefore, the Idsat of the thick gate NMOS devices, for the relatively small gate drive of VDD, is also small. If, as in the example case, N310 must drive node HVA 60 against P318 during a transition, then the reduced Idsat of N310 will cause a long transition delay. Further, as device geometry is reduced, the design of the prior art circuit cannot scale. At some point, the low voltage supply VDD 72 will be too small to effectively switch ON the high voltage NMOS devices N310 and N414.
Referring now to FIG. 2, a second prior art circuit is illustrated. This circuit attempts to overcome the disadvantageous of the first circuit by eliminating the high voltage transistors. In this case, 2-Volt transistors are used to drive a 3.3 Volt output level. Cascaded PMOS transistors P2114 and P3126 are used in the shifting circuit. By biasing the the gate voltages of P2114 and P3126 to VBIAS, HVB 168 is limited to between about 1.6 Volts and 3.3 Volts. This protects the output device P6142 from overstress. While this approach avoids the scaling problem of FIG. 1 by using 2-Volt NMOS devices, that have lower thresholds than 3.3 Volt devices, the addition of the bias circuit to generate VBIAS 150 requires additional devices, consumes extra power, and requires even more circuits to shut down in sleep mode.
Referring now to FIG. 3, another prior art level shifting circuit is shown. This circuit uses what is called a pump-hopping scheme. A signal voltage doubler 170 is used to pump up the differential signals IND 178 and INDB 174 to twice the VDD 72 level. A conventional level shifter using high voltage devices is then used to transform these pumped up differential signals to a single-ended output, OUT 68. This approach doubles the effective VDD and thus reduces the gap between VDD and the threshold voltage (Vt) of the 3.3 Volt NMOS devices. However, it takes about 5 nanoseconds in the worst PVT condition for the pumped differential to switch. This can be too slow for applications above several hundred MHz. In addition, if the input does not switch for some time, pumped charges will leak because of junction reversed-bias leakage. This will cause the doubled voltage to drop to VDD and makes the circuit susceptible to noise.
Several prior art inventions describe circuits for level shifting in low voltage CMOS applications. U.S. Pat. No. 5,539,334 to Clapp, III et al describes a voltage level shifting circuit where NMOS and PMOS transistors are stacked to sustain a higher voltage drop. The stacked devices are biased at a constant fraction of VCC. U.S. Pat. No. 5,821,800 to Le et al discloses a high voltage CMOS level shifter using NMOS/PMOS series intermediate pairs to divide the high voltage supply range into two or more sub-ranges. The pairs are biased to fractions of the high voltage. U.S. Pat. No. 5,963,061 to Briner teaches a level shifter circuit using stacked NMOS/PMOS devices biased to VCC to minimize transistor exposure to high voltage. U.S. Pat. No. 6,002,290 to Avery et al describes a criss-cross voltage level shifter using cascaded devices biased to VDD.
Finally, Co-pending U.S. patent application Ser. No. 09/784,823 (TSMC-00-067) to Wang et al filed on Feb. 20, 2001, teaches a level shifting circuit using zero threshold NMOS devices.
A principal object of the present invention is to provide a level shifting circuit, that is, a circuit that allows a digital signal to be level shifted from a low voltage supply to a high voltage supply.
A further object of the present invention is to provide a level shifting circuit to interface ultra-deep sub-micron CMOS circuits with I/O circuits.
Another further object of the present invention is to provide a level shifting circuit with high switching speed.
Another further object of the present invention is to provide a level shifting circuit with high reliability.
Another further object of the present invention is to provide a level shifting circuit with no static current draw.
Another further object of the present invention is to provide a level shifting circuit with no additional processing step costs compared to the standard CMOS process.
In accordance with the objects of this invention, a level-shifting circuit is achieved comprising, first, a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor. The gates of both of these NMOS transistors are coupled to a low voltage input signal. The drain of the first NMOS transistor is coupled to the source of the first zero threshold NMOS transistor. Second, a second cascaded switch is used. The second cascaded switch comprises a second NMOS transistor and a second zero threshold NMOS transistor. The gates of both of these second NMOS transistors are coupled to an inversion of the low voltage input signal. The drain of the second NMOS transistor is coupled to the source of the second zero threshold NMOS transistor. Finally, a cross-coupled pullup is used. The cross-coupled pull-up comprises a first PMOS transistor and a second PMOS transistor. The sources of both of these PMOS transistors are coupled to a high voltage supply. The gate of the second PMOS transistor and the drain of the first PMOS transistor are coupled to the drain of the first zero threshold NMOS transistor to form an inverted output. The gate of the first PMOS transistor and the drain of the second PMOS transistor are coupled to the drain of the second zero threshold NMOS transistor to form a non-inverted output.
Also in accordance with the objects of this invention, a level-shifting circuit is achieved comprising, first, a first cascaded switch comprising a first NMOS transistor, a first biased NMOS transistor, and a first zero threshold NMOS transistor. The gates of the first NMOS transistor and the first zero threshold NMOS transistor are coupled to a low voltage input signal. The first biased NMOS transistor is coupled between the drain of the first NMOS transistor and the source of the first zero threshold NMOS transistor. The gate of the first biased NMOS transistor is coupled to a constant voltage. Second, a second cascaded switch is used. The second cascaded switch comprises a second NMOS transistor, a second biased NMOS transistor, and a second zero threshold NMOS transistor. The gates of the second NMOS transistor and the second zero threshold NMOS transistor are coupled to an inversion of the low voltage input signal. The second biased NMOS transistor is coupled between the drain of the second NMOS transistor and the source of the second zero threshold NMOS transistor. The gate of the second biased NMOS transistor is coupled to the constant voltage. Finally, a cross-coupled pull-up is used. The cross-coupled pull-up comprises a first PMOS transistor and a second PMOS transistor. The sources of both of these PMOS transistors are coupled to a high voltage supply. The gate of the second PMOS transistor and the drain of the first PMOS transistor are coupled to the drain of the first zero threshold NMOS transistor to form an inverted output. The gate of the first PMOS transistor and the drain of the second PMOS transistor are coupled to the drain of the second zero threshold NMOS transistor to form a non-inverted output.
Also in accordance with the objects of this invention, a method to level-shift a signal is achieved. The method comprises generating an inversion of a low voltage input signal from a low voltage input signal. An inverted output and a non-inverted output are generated from the low voltage input signal and the inversion of said low voltage input signal using a circuit comprising, first, a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor. The gates of both NMOS transistors are coupled to the low voltage input signal. The drain of the first NMOS transistor is coupled to the source of the first zero threshold NMOS transistor. Second, a second cascaded switch is used comprising a second NMOS transistor and a second zero threshold NMOS transistor. The gates of both NMOS transistors are coupled to the inversion of the low voltage input signal. The drain of the second NMOS transistor is coupled to the source of the second zero threshold NMOS transistor. Finally, a cross-coupled pull-up is included comprising a first PMOS transistor and a second PMOS transistor. The sources of both PMOS transistors are coupled to a high voltage supply. The gate of the second PMOS transistor and the drain of the first PMOS transistor are coupled to the drain of the first zero threshold NMOS transistor to form an inverted output. The gate of the first PMOS transistor and the drain of the second PMOS transistor are coupled to the drain of the second zero threshold NMOS transistor to form a non-inverted output.